Programme Details

🏆 denotes Best Paper Award Nominees

Monday   
09:00Welcome
09:15KeynoteVivienne Sze, MIT [Bio]Energy-Efficient Edge Computing for AI-driven Applications [Abstract]
10:15Coffee

 Session M1A:
Design Tools
 Session M1B:
ML Architectures
 
10:55Xuegong Zhou, Lingli Wang, Peiyi Zhao and Alan Mishchenko🏆 Fast Adjustable NPN Classification Using
Generalized Symmetries [pdf]
Andrew Boutros, Sadegh Yazdanshenas and Vaughn Betz🏆 Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs [pdf]
11:20Henri Fraisse and Dinesh Gaitonde🏆 A SAT-based timing driven Place and Route flow for critical soft IP [pdf] Bogdan Pasca and Martin LanghammerActivation Function Architectures for
FPGAs [pdf]
11:45Chirag Ravishankar, Dinesh Gaitonde and Trevor BauerPlacement Strategies for 2.5D FPGA Fabric Architectures [pdf]Peng Guo, Hong Ma, Ruizhi Chen, Pin Li, Shaolin Xie and Donglin WangFBNA: A Fully Binarized Neural Network Accelerator [pdf]
11:52Yehdhih Moctar, Mirjana Stojilovic and Philip BriskDeterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model [pdf]Mihailo Isakov, Alan Ehret and Michel KinsyClosNets: Batchless DNN Training with On-Chip A Priori Sparse Neural Topologies [pdf]
11:59Dries Vercruyce, Elias Vansteenkiste and Dirk StroobandtHierarchical Force-Based Block Spreading for Analytical FPGA Placement [pdf]Cheng Luo, Yuhua Wang, Wei Cao, Philip Leong and Lingli WangRNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks [pdf]
12:06Alex Rodionov and Jonathan RoseAutomatic Topology Optimization for FPGA Interconnect Synthesis [pdf]Di Wu, Jin Chen, Lingli Wang and Wei CaoA Novel Low-Communication Energy Efficient Reconfigurable CNN Acceleration Architecture for Embedded Systems [pdf]

12:15Lunch

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  Monday afternoon sessions

13:30KeynoteBrendan Farley, Xilinx [Bio]Implementing Software Defined Radios for 5G with Next Generation FPGA’s. [Abstract]

 Session M2A: Runtime Methods Session M2B: Machine Learning Architectures 
14:35Ibrahim Ahmed, Shuze Zhao, James Meijers, Olivier Trescases and Vaughn Betz🏆 Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs [pdf]Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn and Michaela BlottFINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs [pdf]
15:00Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach and Krste AsanovicDESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles [pdf]Julian Faraone, Giulio Gambardella, David Boland, Nicholas Fraser, Michaela Blott and Philip LeongCustomizing Low-Precision Deep Neural Networks For FPGAs [pdf]
15:07Robert Hale and Brad HutchingsEnabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs [pdf]Yongming Shen, Tianchu Ji, Michael Ferdman and Peter MilderScalable Memory Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces [pdf]
15:14Behzad Salami, Osman Unsal and Adrian CristalFault Characterization Through
FPGA Undervolting [pdf]
Eriko Nurvitadhi, Jeff Cook, Asit Mishra and Debbie MarrIn-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC [pdf]
15:25Posters/Coffee

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  Monday late afternoon sessions

 Session M3A:
Cloud/Databases
 Session M3B:
Machine Learning Frameworks
 
16:25Anuj Vaishnav, Khoa Pham, Dirk Koch and James GarsideResource Elastic Virtualization for FPGAs using OpenCL [pdf]Jiandong Mu, Wei Zhang, Hao Liang and Sharad SinhaA Collaborative Framework for FPGA-based CNN Design Modeling and Optimization [pdf]
16:50Zsolt Istvan, Gustavo Alonso and Ankit SinglaProviding Multi-tenant Services with FPGAs: Case Study on a Key-Value Store [pdf]Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk and Xinyu NiuTowards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA [pdf]
17:15Philippos Papaphilippou and Wayne LukAccelerating database systems using FPGAs: A survey [pdf]Alexandros Kouris, Stylianos I. Venieris and Christos-Savvas BouganisCascadeCNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks [pdf]
17:40Anuj Vaishnav, Khoa Pham and Dirk KochA Survey on FPGA Virtualization [pdf]Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin and Deming ChenA Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA [pdf]

18:30 Welcome reception

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Tuesday     
09:15KeynoteDan Werthimer,
SETI and University
of California Berkeley [Bio]
Searching for E.T. with FPGAs [Abstract]
10:15Coffee

 Session T1A:
Networking and Connectivity
 Session T1B:
High Performance Applications
 
10:45Athanasios Stratikopoulos, Christos Kotselidis, John Goodacre and Mikel LujanFastPath: Towards Wire-speed NVMe SSDs [pdf]Krystine Dawn Sherwin (Tyrone Sherwin), Kevin I-Kai Wang, Prabu Thiagaraj and Oliver SinnenMedian filtering with very large windows: SKA algorithms for FPGAs [pdf]
11:10Andreas Oeldemann, Thomas Wild and Andreas HerkersdorfFlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet [pdf]Nikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos and Dionisios Pnevmatikatos🏆 Accelerated Inference of Positive Selection on Whole Genomes [pdf]
11:35Shanker Shreejith, Ryan A. Cooke and Suhaib A FahmyA Smart Network Interface Approach for Distributed Applications on Xilinx Zynq SoCs [pdf]Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei and Tianhe YuSMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing [pdf]
11:42Qingqing Xiong, Anthony Skjellum and Martin HerbordtAccelerating MPI Message Matching through FPGA Offload [pdf]Nina Engelhardt, C.-H. Dominic Hung and Hayden Kwok-Hay SoPerformance-driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems [pdf]
11:49Jiayi Sheng, Chen Yang and Martin HerbordtHigh Performance Communication on Reconfigurable Clusters [pdf]

12:00Lunch

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  Tuesday afternoon sessions
13:30KeynoteLinda Doyle,
Dean of Research
Trinity College Dublin [Bio]
The future of communications and its computational landscape

 Session T2A:
Dynamic Reconfiguration
 Session T2B:
Architecture
 
14:35Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew Kei Lam and Nandeesha VeerannaCIDPro: Custom Instructions for Dynamic Program Diversification [pdf]Ameer M.S. Abdelhadi, Lesley Shannon and Guy LemieuxModular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories MOVED TO WED AFTERNOON
15:00Marie Nguyen and James HoeTime-Shared Execution of Streaming Pipelines by Dynamic Partial Reconfiguration [pdf]Lake Bu and Michel KinsyWeighted Group Decision Making Using Multi-identity Physical Unclonable Functions [pdf]
15:07Dongjoon Park, Yuanlong Xiao, Nevo Magnezi and Andre DehonCase for Fast FPGA Compilation using Partial Reconfiguration [pdf]Ankit Wagle, Jinghua Yang, Aykut Dengi and Sarma VrudhulaFPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area [pdf]
15:14Takuya Kojima and Hideharu AmanoA Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures [pdf]Dustin Richmond and Ryan KastnerEveryone's a Critic: A Tool for Exploring RISC-V Projects [pdf]

15:25Posters/Coffee

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  Tuesday late afternoon sessions

 Session T3A: High Level Synthesis Session T3B: Machine Learning 
16:25Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf and Andreas KochILP-based Modulo Scheduling and Binding for Register Minimization [pdf]Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu and Wayne LukReconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation [pdf]
16:50Charles Lo and Paul ChowMulti-Fidelity Optimization for High-Level Synthesis Directives [pdf]Muhsen Owaida and Gustavo Alonso🏆 Application Partitioning on FPGA Clusters: Inference over Decision Tree Ensembles [pdf]
17:15Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Oliver Sinnen and Andreas KochDependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis [pdf]Jia Liu and Qiang LiuResource Reduction of BFGS Quasi-Newton Implementation on FPGA using Fixed-Point Matrix Updating [pdf]

18:30 Conference Banquet

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Wednesday     
09:15KeynoteMarilyn Wolf,
Georigia Institute of Technology [Bio]
IoT Systems Caring Analytics for Long-Term Care of People with Special Needs [Abstract]
10:15Coffee

 Session W1A: Arithmetic Session W1B: Computer Vision and Graphics 
11:00Yaman Umuroglu, Lahiru Rasnayake and Magnus Själander🏆 BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing [pdf]Michael Barrow, Steven Burns and Ryan KastnerA FPGA Accelerator for Real-Time 3D Non-Rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation [pdf]
11:25François Serre and Markus Püschel🏆 A DSL-based FFT hardware generator in Scala [pdf]Georgios Chatzianastasiou and George A. ConstantinidesAn Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics [pdf]
11:50Debapriya Basu Roy and Debdeep MukhopadhyayRevisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p) [pdf]Murad Qasaimeh, Joseph Zambreno and Phillip JonesA Runtime Configurable Hardware Architecture for Computing Histogram-based Feature Descriptors [pdf]
11:57Luis Fiolhais and Horacio NetoAn Efficient Exact Fused Dot Product Processor in FPGA [pdf]Tobias Alonso, Mario Ruiz, Angel López García-Arias, Gustavo Sutter and Jorge E. López de VergaraSubmicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip [pdf]
12:04Ahmet Can Mert, Hasan Azgin, Ercan Kalali and Ilker HamzaogluEfficient Multiple Constant Multiplication Using DSP Blocks in FPGA [pdf]

12:15Lunch

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  Wednesday afternoon sessions
13:30KeynotePatrick Dorsey,
Intel [Bio]
SiP Integration of Reusable Chiplets [Abstract]

 Session W2A:
Design Approaches
 Session W2B:
Machine Learning - Tools
 
14:35Mustafa Abbas and Vaughn BetzLatency Insensitive Design Styles for FPGAs [pdf]Stylianos Venieris and Christos Bouganisf-CNNx: A Toolflow for Mapping Multiple Convolutional Neural Networks on FPGAs [pdf]
15:00Zhenhao He, David Sidler, Zsolt Istvan and Gustavo AlonsoA Flexible K-Means Operator for Hybrid Databases [pdf]Andreea Ingrid Cross, Liucheng Guo, Wayne Luk and Mark SalmonCRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems [pdf]
15:07Jonathan Dechelotte, Russell Tessier, Dominique Dallet and Jeremie CrenneA lightweight software layer for rapid SoC FPGA prototyping [pdf]Tong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang, Rushi Patel and Martin HerbordtA Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Workload Balancing [pdf]
15:14Sam Amiri, Mohammad Hosseinabady, Andres Rodriguez, Rafael Asenjo, Angeles Navarro and Jose Nunez-YanezWorkload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips [pdf]Mário Véstias, Rui Policarpo Duarte, Jose Sousa and Horacio NetoLite-CNN: A High-Performance Architecture to Run CNNs in Low Density FPGAs [pdf]

15:25Posters/Coffee

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  Wednesday late afternoon sessions

 Session W3A:
Overlays/CGRAs
 Session W3B:
Machine Learning and Model Checking
 
16:25Al-Shahna Jamal, Jeffrey Goeders and Steve WiltonAn FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug [pdf]Gary Grewal, Shawki Areibi, Anthony Vannelli, Ziad Abouwaimer, Timothy Martin, Dani Maarouf, Abeer Al-Hyari and Andrew Gunter🏆 Machine-Learning Based Congestion Estimation for Modern FPGAs [pdf]
16:50Mohamed Abdelfattah, Andrew Ling, Andrew Bitar, David Han, Roberto Dicecco, Nitika Shanker, Joseph Chu, Shane O'Connell and Gordon ChiuDLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration [pdf]Shenghsun Cho, Michael Ferdman and Peter MilderFPGASwarm: High Throughput Model Checking Using FPGAs [pdf]
17:15Thiem Van Chu and Kenji KiseAn Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs [pdf]Ameer M.S. Abdelhadi, Lesley Shannon and Guy LemieuxModular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories [pdf]

 PhD Forum 
17:45Yao Liu, Ray Cheung and Hei WongLightweight secure processor prototype on FPGA [pdf]
17:50Jan Kuehn and Yiannos ManoliAn Application-Specific Field-Programmable Tree Ensemble Architecture [pdf]
17:55Umar Minhas, Roger Woods and Georgios KarakonstantisFacilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems [pdf]
18:00Habib Ul Hasan Khan and Diana GöhringerCycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs using Artificial Intelligence [pdf]
18:40 – 20:00 PhD Forum and Demo night
Demo night papers 
Behzad Salami, Osman Unsal
and Adrian Cristal
A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs
[pdf]
Declan Byrne, Ronan Farrell and John DooleyDigital Pre-Distortion Implementation on FPGA & FMCOMMS2
[pdf]
Lukáš Kekely, Martin Špinler,
Štepán Friedl, Jiří Sikora
and Jan Kořenek
Accelerated Wire-Speed Packet Capture at 200 Gbps
[pdf]
Hiroki Nakahara, Masayuki Shimoda
and Shimpei Sato
A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2)
[pdf]
Fearghal Morgan, Frank Callaly,
Declan O'Loughlin, Jeremy Audiger,
Yohan Boyer and Niall Timlin-Canning
viciLogic: Learn and Prototype Chip Design Online
[pdf]
Masayuki Shimoda, Shimpei Sato
and Hiroki Nakahara
Demonstration of Object Detection for an event-driven camera
[pdf]
Simone Casale Brunet,
Thierry Schuepbach,
Nicolas Guex, Christian Iseli,
Alan Bridge, Dmitry Kuznetsov,
Christian Sigrist, Philippe Lemercier,
Ioannis Xenarios and Endri Bezati
Towards in the field fast pathogens detection using FPGAs
[pdf]
Yi ShanADAS and Video Surveillance Analytics System using Deep Learning Algorithms on FPGA [pdf]

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Thursday/Friday    
Workshops and Tutorials